1. Field of the Invention
The present invention relates to a driving-device for a display device which, for example, can be preferably incorporated in a liquid crystal display device or the like device.
2. Description of Related Art
FIG. 1 is a block diagram showing a basic construction of a conventional liquid crystal display device 101. A display panel 102 comprises a pair of transparent substrates, the substrates being spaced from each other with a liquid crystal layer therebetween. A plurality of common electrodes and segment electrodes are provided on a surface of each transparent substrate facing the liquid crystal layer. The display panel 102 is divided into a plurality of display regions (for example 2) 103a, 103b. The segment electrodes constituting the display region 103a are driven by a first segment electrode driving circuit 105a. The segment electrodes constituting the display region 103b are driven by a second segment electrode driving circuit 105b. The common electrodes are driven by a common electrode driving circuit 104.
The common electrode driving circuit 104, the first segment electrode driving circuit 105a and the second segment electrode driving circuits 105b are driven in accordance with display control data sent from a central processing unit (hereinafter referred to as CPU) 106. The common electrode driving circuit 104 comprises a display controller 107, calculation section 108, and a clock generating circuit 109.
The CPU 106 feeds the display control data to the common electrode driving circuit 104. The calculation section 108 of the common electrode driving circuit 104 is adapted to calculate information indicative of the designated display region where display data is to be displayed and display address information in the designated display region in accordance with the display control data fed from the CPU 106.
The display controller 107 selects either of the first segment electrode driving circuit 105a or the second segment electrode driving circuit 105b in accordance with the display region designating information, and feeds the display address information to the selected segment electrode driving circuit. The display controller 107 selects the common electrode in accordance with the display address information, and applies a voltage to the selected common electrode. Further, the selected segment electrode driving circuit selects the segment electrode in accordance with the display address information, and applies a voltage to the selected segment electrode. In such a manner as described above, display operation is executed on the display panel 102.
The display controller 107 and the calculation section 108 execute their respective operations, in synchronization with a clock signal sent from the clock generating circuit 109. The clock signal generating circuit 109 comprises a CR oscillator. A resistor 110 is externally attached to the clock signal generating circuit 109, which sends a clock signal having, for example, a frequency of about 32 kHz.
In the common electrode driving circuit 104 of the liquid crystal display device 101, the clock signal generating circuit 109 sends a relatively low speed clock signal to the calculation section 108 as well as the display controller 107 so as to execute the calculation operation. This presents a problem that the calculation operation is executed at a low speed. Particularly, in order to effect a function accompanied by a complex processing, such as a window function and an address converting function, the clock signal for controlling the display is too slow for the calculation section 108 to execute the calculation operation. Accordingly, there are some cases where the calculation section 108 cannot be suited for actual use.
The window function is a function for displaying a different display data in a specific display region set in the display region on a display screen where an display data is already displayed.
Further, in the case where the frequency of the clock signal is amplified so as to execute the calculation operation at a high speed, the liquid crystal display device consumes more power. Particularly, for example, in a portable electronic device called generally as an electronic notebook, the power is supplied by cells. Accordingly, the life of the cells is shortened, which presents a problem.
A liquid crystal display device of a simple matrix type comprises a plurality of electrodes formed in both a row direction and a column direction interlaced with each other on a pair of transparent substrates. Each row direction electrode is scanned by a column direction driving circuit along the column direction. Each column direction electrode is scanned by a row direction driving circuit along the row direction. A display signal is sent each time the scanning is completed for each row direction electrode. The row direction driving circuit and the column direction driving circuit execute the respective foregoing operations in accordance with the display signal and a scan signal from a central processing unit (CPU).
Liquid crystal is filled between the row direction electrodes and the column direction electrodes. In order to prevent an occurrence in which a direct current is applied to the liquid crystal, the display signal is added onto an inversion signal whose polarity periodically inverts and alternated in the CPU, and applied to the liquid crystal with the polarity thereof inverting periodically.
An example of the inversion signal FRM is shown in FIG. 2(2). FIG. 2(1) shows a timing sequence diagram of a clock signal generated in the CPU. The inversion signal FRM is generated by counting the number of clocks corresponding to a duty (e.g., 1/146 DUTY) of the operation of the row direction driving circuit and causing the polarity thereof to invert by a toggling operation. More specifically, a clock signal LCK shown in FIG. 2(1) is counted by a counter or the like provided in the CPU. Upon the first fall of the clock signal LCK, the inversion signal LCK switches from a low level to a high level.
Thereafter, 146 clock signals LCK are counted, and the inversion signal FRM switches from the high level to the low level upon the 146th fall of the clock signal LCK. The inversion signal is generated by executing the toggling operation in a similar manner.
In the conventional liquid crystal display device utilizing the inversion signal FRM described above, in the case where a character "F" is to be displayed as illustrated in FIG. 3, it is known that an error display 112 represented by a broken line in FIG. 3 occurs below a lighted display region 111 on a lower portion of the column direction electrode having many lighted addresses in the column direction of the liquid crystal display device 101, i.e., in a Y-direction in FIG. 3. Such an error display 112 causes the quality of the display of the liquid crystal display device 101 to deteriorate greatly.
FIG. 4 is a diagram showing an electrical construction of a conventional liquid crystal display device 201 of a typical type. The liquid crystal display device 201 comprises a matrix driven liquid crystal element 202, a column direction driving circuit 203 for scanning the liquid crystal element 201 in the column direction, and a row direction driving circuit 204 for scanning the liquid crystal element 201 in the row direction and outputting the display data. The display data outputted from a display data output unit 205 provided in the row direction driving circuit 204 has its voltage level converted by a level shifter 206, for example, from a transistor level to a drive level of the liquid crystal element 202. The outputs from the level shifter 206, both inverted and non-inverted, are respectively connected to pairs of NAND circuits 207, 208, and NOR circuits 209, 210.
To the row direction driving circuit 204 is sent from outside the inversion signal FRM for alternating the display voltage. An inversion signal FRM' (obtained by amplifying the inversion signal FRM by a level shifter 211) is sent to the NAND circuits 207, 208, and the NOR circuits 209, 210 individually, respectively. In the row direction driving circuit 204, four mutually different kinds of driving voltagles V1 to V4 are generated to be applied to the liquid Crystal element 202. The respective potentials V1 to V4 are individually coupled to switching circuits 212, 213 comprising respectively transistors having a P-channel metal oxide semiconductor (MOS) structure, switching circuits 214, 215 comprising respectively transistors having a N-channel MOS structure. Outputs from the respective switching circuits 212 to 215 are inputted to the liquid crystal display element 202 through a common line 216.
In the row direction driving circuit 204 thus constructed, the switching circuits 212 to 215 receive outputs respectively from the NAND circuits 207, 208, and NOR circuits 209, 210. The outputs of the NAND circuits 207, 208, and NOB circuits 209, 210 depend on the four combinations based on whether the waveform of the data from the level shifter 206 is high level or low level, or whether the inversion signal FRM' is high level or low level. The logic circuits and the switching circuits are so controlled that when any one pair of logic circuit and switching circuit are communicating, the other remaining pairs are kept out of communication.
In the crystal display device of this prior art, when the polarity of the inversion signal FRM is converted from a high level to a low level or vice-versa, an overlapping period occurs during which the respective switching circuits 212 to 215 are simultaneously turned on based on the difference in response to the level conversion of the signal FRM between the P-channel switching circuits 212, 213 and the N-channel switching circuits 214, 215, i.e., on the characteristics that the P-channel switching circuits 212, 213 respond less quickly than the N-channel switching circuits 214, 215. Thereby, the respective driving voltages V1 to V4 are simultaneously connected to the common line 216, whereby the current flows through the common line 216. Accordingly, power consumption of the row direction driving circuit 204 is increased. Further, it stands as a problem that the row direction driving circuit 204 is liable to meet a damage due to the current flowing through the common line 216.
The display voltage based on the display data is applied to the liquid crystal layer filled between the row direction electrodes and the row direction electrodes so as to execute the display operation. In order to improve such display characteristics in the liquid crystal display device, the method is adopted by which plural kinds of driving voltages are generated in the liquid crystal display device, the desired driving voltage is selected out of the plural ones, and the level of the display signal is adjusted to the selected driving voltage.
FIG. 5 is a circuit diagram of a display power circuit 121 of a typical prior art device. The display power circuit 121 comprises a variable resistor VR having one end thereof connected to a display power voltage VE, and resistors, for example 5, R1, R2, R3, R4, and R5 connected to the other end of the variable resistor VR. The resistors R1 to R5 are connected in series to one another. Respective outputs from nodes P1, P2, P3, P4, and P5 between the variable resistor VR and the respective resistors R1, R2, R3, R4, and R5 are inputted to amplifiers A1, A2, A3, A4, and A5, and the driving currents are amplified therein. Consequently, a plurality of mutually different display voltages V1, V5, V3, V4, and V6 are respectively outputted from the amplifiers A1, A2, A3, A4, and A5. An output from a node P6 between the variable resistor VR and a grounded side of the resistor R5 is used as a display voltage V2.
The resistors R1, R2, R3, R4, and R5 for dividing the voltage are referred to as bleeder resistors, and respectively takes resistance values r1, r1, r2, r1, and r1. With the use of resistance values r1, r2, and the resistors R1, R2, R3, R4, and R5, an optimum bias voltage value Vbi can be expressed based on the driving duty DUTY of the liquid crystal display device in the following first equation. ##EQU1##
More specifically, in the case where the driving duty of the liquid crystal display device of this prior art is, for example, 1/146 DUTY, the optimum bias voltage value Vbi is obtained from the first equation (1): ##EQU2##
Accordingly, the following third expression is obtained: EQU R2=9.times.R1 (3)
Therefore, the ratio of the voltage divided by the respective resistors R1 to R5 is 1:1:9:1:1. The display voltage level is thus determined.
FIG. 6 is a diagram showing an operation of the liquid crystal display device of this prior art device. In the case where contrast adjustment is not to be effected in the display power circuit 121, the resistance value r of the variable resistor VR is set at "0". The display voltage V1, which is the maximum in the display voltages V1 to V6, corresponds with the display power voltage VE. FIG. 6(A) shows a case where the contrast adjustment is effected with the use of the display power circuit 121, and the resistance value r of the variable resistor VR is set at a non-zero arbitrary value. In this case, the maximum display voltage V1 is reduced from the display power voltage VE by a potential difference .DELTA.V. The level of the remaining voltages V2 to V6 are also reduced with the ratio of potentials therebetween maintained at V1-V5:V5-V3:V3-V4:V4-V6:V6-V2=1:1:9:1:1 as shown in FIG. 6(A).
On the other hand, in the case where the contrast adjustment is not to be effected in the display power circuit 121, the maximum display voltage V1 is supposed to correspond with the display power voltage VE. However, it is generally known that the maximum value of the display voltage V1 is lower than the display power voltage VE by a potential difference .delta.V of about 2 to 3 V due to the characteristics of the amplifier A1. The maximum display voltage V1 in this state is shown with a broken like in FIG. 6(B). In the case where the maximum display voltage V1 is reduced to an undesirable level, the potentials of the display voltages V1 to V6 cannot be maintained at the foregoing ratio. Accordingly, the quality of the display will be undesirably deteriorated.
In view of this, the liquid crystal display device of this prior art presents a problem that the quality of the display will be deteriorated in the case where the contrast adjustment is not effected.
FIG. 7 is a partially circuit diagram and partially block diagram showing a basic construction of another conventional liquid crystal display device 301. A display unit 302 comprises a pair of transparent substrates provided with a liquid crystal layer therebetween. A plurality of the common electrodes and segment electrodes are disposed on surfaces of the respective transparent substrates facing the liquid crystal layer. The common electrodes and the segment electrodes are respectively driven by a common electrode driving circuit 303 and a segment electrode driving circuit 304.
A central processing unit (hereinafter referred to as a CPU) 305 is adapted for centrally controlling the liquid crystal display device 301. The CPU 305 sends display data to the common electrode driving circuit 303, and then to the segment electrode driving circuit 304. Based on the display data sent from the CPU 305, the common electrode driving circuit 303 and the segment electrode driving circuit 304 respectively select the common electrodes and the segment electrodes, and apply the voltages to the selected electrodes.
A power circuit 306 feeds liquid crystal driving voltages V1, V2, V5, and V6 to the common electrode driving circuit 303. The power circuit 306 also feeds liquid crystal driving voltages V1, V2, V3 and V4 to the segment electrode driving circuit 304. In the power circuit 306, a voltage reel supplied from a power source 307 is adjusted by a variable resistor 309 to a voltage Vee2, which is fed to an applied voltage generating circuit 310. Between the power supply 307 and the variable resistor 309 is provided a switch 308, which is turned off upon receiving an OFF signal S11 from the CPU 305. This causes the power supply from the power source 307 to the applied voltage generating circuit 310 to be interrupted.
The applied voltage generating circuit 310 includes five resistors R11a, R11b, R11c, R11d, and R12 so as to divide the voltage Vee2 and generate driving voltages V1 to V6. These five resistors R11a, R11b, R11c, R11d, and R12 are generally referred to as bleeder resistors. The resistors R11a, R11b, R12, R11c, and R11d are connected in series in this order to the variable resistor 309. One end of the resistor R11d is grounded. Resistance values r11a to r11d of the respective resistors R11a to R11d are all set at a same value. A resistance value r12 of the resistor R12 varies according to the driving duty DUTY of the display unit 302 and the optimum bias value b, and can be obtained using the following fourth equation. ##EQU3##
Further, smoothing capacitors C11 to C16 for stabilizing the applied voltages are connected respectively between nodes E1 to E6 and the common electrode driving circuit 303 or the segment electrode driving circuit 304.
Out of the voltages V1 to V6 supplied from the power circuit 306, the voltages V1, V2, V5, and V6 are supplied to the common electrode driving circuit 303, and the voltages V1, V2, V3, V4 are supplied to the segment electrode driving circuit 304.
In the liquid crystal display device 301 described above, the smoothing capacitors C11 to C16 are provided so as to stabilize the voltage level applied to the display unit 302. Even in the case where the switch 308 is turned off to interrupt the power supply from Dower source 307 to the applied voltage generating circuit 310, which in turn causes the display unit 302 to stop displaying, electric charges stored in the capacitors C11 to C16 are gradually discharged in accordance with the discharge characteristics. Accordingly, the voltage is applied to the liquid crystal layer in the display unit 302, whereby, so-called, a residual image is displayed on the display unit 302.